MorphoSys: a Reconfigurable Architecture Optimized for Ray Tracing

This paper describes a new generation of MorphoSys, a s ystem-on-chip that incorporates hardware, supports to achieve interactive ray tracing. It has a matrix of 8x8 SIMD reconfigurable cells (RCs) to facilitate different mapping schemes. We have identified the ray tracing mapping scheme with a good trade-off between speed, power, and bandwidth requirement. A pseudo branch mechanism and local RC stacks are introduced to support the irregular control flow in ray tracing, such as nested if-then-else and recursions. MorphoSys has a Spatial Partitioning Tree (SPT) Buffer that supplies RC array with eight non-streaming data concurrently and relaxes the pressure on the bandwidth by the data-intensive parallel ray traversals. A Pointer Update Unit in the central controller and a Write Buffer between this controller and the stack remove the overhead due to the calculations and stack pushes of large amount of intermediate pointers for parallel depth-first-ray-traversals. Experimental results show that interactive ray tracing is achieved. MorphoSys is a SIMD reconfigurable architecture. It consists of an array of 64 reconfigurable cells (RCs) on the same chip with a general-purpose RISC processor, TinyRISC. It was designed with small size (33mm 2 in 0.13um) and low frequency (300MHz). It supports highly paralleled execution with minimum overhead in data and instruction transfers. Multimedia applications with a mix of sequential tasks and coarse-grain parallelism, requiring computation intensive work and high throughput have been efficiently implemented on it. The reconfiguration is done through loading and executing different instruction streams, called " contexts " , in the 64 RCs, so that the RC array can be dynamically switched between tasks with different data access and communication patterns. The RC array can be configured as 64-way SIMD, eight 8-way SIMD, or just 64-way SISD. Data communications between parallel tasks are through the interconnections between neighboring RCs or among the RCs in the same row or column. A streaming data memory, Frame Buffer and a Context Memory are both organized as double banks. MorphoSys can overlap RC computation with data and context prefetching through DMA. TinyRISC is responsible for controlling RC array execution and DMA transfers. It also executes the sequential parts of an application. MorphoSys has been optimized for ray tracing by incorporating a pseudo branch mechanism, 64 local RC stacks, a SPT Buffer, a Pointer Update Unit and a Write Buffer. Ray tracing is a 3D graphics algorithm for realistic image generation. It calculates the accurate image colors …